Office Hours: by appointment in Levine 572
Class discussion and announcements are via Piazza
Tuesday/Thursday 10:30-12:00noon, Towne 307
The transition to multicore architectures raises new security issues that are not present with uniprocessors. Mutually untrusting workloads running concurrently on distinct cores can interfere with each other via shared structures like caches and memory controllers. This seminar will cover in detail research literature on the sources of interference, the attacks they make possible, and mitigation techniques. Graduate-level coursework in computer architecture (CIS 501) will be very helpful.
No textbooks are required; links to all the papers we read will be provided at this website.
There will be no exams.
Submit homework, reading quizzes and future-work write-ups via Canvas.
The class project can be done in groups of 2-3. The project is open-ended: it should be something related to information flow or performance isolation in multicores but the specifics are up to you. Choosing a project that incorporates your existing research is a great idea!
This schedule is subject to change
Many of the paper links below are to publisher sites (like the ACM Digital Library). You’ll need to download the papers from an on-campus computer or via the UPenn Library proxy.