CIS 4710/5710: Computer Organization and Design Spring 2024

![RISC-V Urania Chip from ETH Zurich and the University of Bologna](images/riscv-pulp-urania.jpg "RISC-V Urania Chip from ETH Zurich and the University of Bologna")  <h2>CIS 4710/5710: Computer Organization and Design <small>Spring 2024</small></h2> ### Course Information **instructor**: [Joe Devietti](http://www.cis.upenn.edu/~devietti/) **when**: MW 10:15-11:45am **where**: [Meyerson B1](https://www.facilities.upenn.edu/maps/locations/meyerson-hall) **contact**: [canvas](https://canvas.upenn.edu/courses/1774526) (has links to Gradescope and Ed Discussions) **homework**: [github](https://github.com/cis5710/cis5710-homework) **TAs**: + Chengjun Li + Elizabeth Martinez + Jerry Wang + Kaitlyn Lu + Lyndsey Barrett + Nathan Sobotka + Naveen Albert + Ryan Oliver + Soyoon Park + Zhijing Yao **office hours** We use OHQ to manage office hours, [our class queue is here](https://ohq.io/courses/733). Some OH are in-person, some virtual via Zoom. See the Pinned post on Ed Discussions for OH details. ### Course Description This is a second computer organization course and focuses on computer hardware design. In this course you will design and implement a pipelined processor for the RISC-V ISA using SystemVerilog. You will learn the range of architectural techniques used in modern CPU design including superscalar design, out-of-order execution, and cache hierarchies. ### Frequently Asked Questions * What's the difference between CIS 4710 and CIS 5710? There is **no** difference in the course content (assignments, exams, etc.) between CIS 4710 and 5710. If you are a graduate student, however, you'll need to take CIS 5710. * Do all group partners need to be in the **same** course number? No, one member can be in CIS 4710 while the other is in CIS 5710. ### Prerequisites Undergraduate students need to have completed CIS 2400. Graduate students should be familiar with assembly language programming (the language is not so important, all assembly languages are pretty similar), digital circuits (muxes, adders, flip-flops and simple sequential circuits), binary numbers, 2's complement arithmetic, and knowledge of at least one software programming language. This course does not assume any prior experience with SystemVerilog. ### Course Materials There are no required textbooks. The most relevant textbook is *Computer Organization and Design: The Hardware/Software Interface* by Patterson and Hennessy. The 4th and 5th Editions are both fine. The 4th Edition is available [for free on-line through the Penn Library](http://hdl.library.upenn.edu/1017.12/876659). *Introduction to Logic Synthesis using Verilog HDL* by Reese and Thornton is also a nice introduction to hardware design and Verilog. It is also available [as a free PDF via the Penn Library](https://link-springer-com.proxy.library.upenn.edu/book/10.1007/978-3-031-79743-9). I also like [*Digital Design: A Systems Approach*](https://www.cambridge.org/us/academic/subjects/engineering/circuits-and-systems/digital-design-systems-approach?format=HB&isbn=9780521199506) by Dally and Harting. I'm not aware of a free version, unfortunately. It gives a nice explanation of many of the topics we'll cover in class. The official [RISC-V ISA Specification](https://drive.google.com/file/d/1s0lZxUZaa7eV_O0_WsZzaurFLLww7ou5/view?usp=drive_link) and our [RISC-V ISA quick-reference sheet](https://github.com/cis5710/cis5710-homework/blob/main/riscv%20isa%20reference%20sheet.pdf) will also be useful. ### Course Policies See details about [course policies on late days, collaboration, etc.](policies.html) ### Lecture slides Lecture recordings are available *only with justification*, via Canvas under **Class Recordings**. Lecture slides: + Introduction ([pptx](slides/01_intro.pptx), [pdf](slides/01_intro.pdf)) + RISC-V ([pptx](slides/02_riscv.pptx), [pdf](slides/02_riscv.pdf)) + SystemVerilog ([pptx](slides/03_systemverilog.pptx), [pdf](slides/03_systemverilog.pdf)) + Arithmetic ([pptx](slides/04_arith.pptx), [pdf](slides/04_arith.pdf)) + Single-Cycle Datapath ([pptx](slides/05_singlecycle.pptx), [pdf](slides/05_singlecycle.pdf)) + Performance ([pptx](slides/06_performance.pptx), [pdf](slides/06_performance.pdf)) + Debugging ([pptx](slides/07_debugging.pptx), [pdf](slides/07_debugging.pdf)) + Verification ([pptx](slides/08_verification.pptx), [pdf](slides/08_verification.pdf)) + Pipelined Datapath ([pptx](slides/09_pipeline.pptx), [pdf](slides/09_pipeline.pdf)) + Branch Prediction ([pptx](slides/10_branchprediction.pptx), [pdf](slides/10_branchprediction.pdf)) + Caches ([pptx](slides/11_caches.pptx), [pdf](slides/11_caches.pdf)) + Memory ([pptx](slides/12_virtual_memory.pptx), [pdf](slides/12_virtual_memory.pdf)) + AXI ([pptx](slides/13_axi.pptx), [pdf](slides/13_axi.pdf)) + Superscalar ([pptx](slides/14_superscalar.pptx), [pdf](slides/14_superscalar.pdf)) + Out-of-Order ([pptx](slides/15_ooo.pptx), [pdf](slides/15_ooo.pdf)) + Multicore ([pptx](slides/16_multicore.pptx), [pdf](slides/16_multicore.pdf)) + Accelerators ([pptx](slides/17_accelerators.pptx), [pdf](slides/17_accelerators.pdf))  ### Course Schedule The course schedule is maintained on our Canvas site. ### Previous Editions - [CIS 4710/5710, Spring 2023](http://cis.upenn.edu/~cis5710/spring2023) - [CIS 471/571, Spring 2022](http://cis.upenn.edu/~cis5710/spring2022) - [CIS 471/571, Spring 2021](http://cis.upenn.edu/~cis5710/spring2021) - [CIS 371, Spring 2020](http://cis.upenn.edu/~cis5710/spring2020) - [CIS 501, Fall 2019](http://cis.upenn.edu/~cis5710/fall2019)