instructor: Joe Devietti
when: Tuesday/Thursday 4:30-6:00pm
where: Berger Auditorium in Skirkanich Hall
contact: piazza, , canvas
TAs: Connie Ho, Jinyan Cao and Laurel Emurian
graders: Huinan Yu, Venkataramanan Arun and Suiyao Ma
Monday 2-3, Levine 614 (Laurel)
Tuesday 1-2pm, Levine 572 (Joe)
Tuesday 3:30-4:30, Moore 100 (Connie)
Wednesday 12-1, Moore 100 (Jin)
Friday 11-12, Moore 100 (Jin)
This course is a graduate course on computer architecture with an emphasis on a quantitative approach to cost/performance design tradeoffs. The course covers the fundamentals of classical and modern processor design: performance and cost issues, instruction sets, pipelining, caches, physical memory, virtual memory, I/O superscalar and out-of-order instruction execution, speculative execution, long (SIMD) and short (multimedia) vector execution, multithreading, and an introduction to shared memory multiprocessors.
CIS 501 is a graduate-level course on computer architecture that assumes significant prior knowledge of computer organization and architecture. You should already be familiar with hardware caches, instruction execution pipelines, basic logic design, and some assembly-level programming. Students are expected to have had a course that covers the material in a textbook such as Patterson and Hennessy’s “Computer Organization and Design: The Hardware/Software Interface”. Penn’s CIS 371 is an example of such a course.
If you do not have the appropriate background, you should either 1) not take this class or 2) spend significant time reviewing the textbook and lecture notes from CIS 371.
The course textbook is Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors by Jean-Loup Baer. Two copies of the textbook are on reserve at the Penn Engineering Library, and there is also an electronic version at Cambridge Books Online that up to 3 students can view at one time from the Penn network.
If you have no undergraduate coursework in computer architecture you may also want to acquire a copy of Patterson and Hennessy’s Computer Organization and Design: The Hardware/Software Interface. The Penn Library provides unlimited access to an online version of this book.
Paper Reviews: 5%
Midterm exam: 30%
Final exam: 45%
There will be a midterm exam and a final exam. The final exam will be cumulative and will be held during the final time slot for the course. The final exam will also count as the PhD Architecture WPE I exam.
There will be several homework assignments, consisting of problems to be worked out by hand and/or coding of simulations. You are granted two 48-hour “grace” periods, and can use at most one per assignment. If you’d like to use a grace period, just email me and I will unlock the assignment on Canvas, no questions asked. No assignment will be accepted after the solutions are posted. Note that grace periods cannot be used for paper reviews.
There will be several paper reviews of academic papers from the computer architecture research literature. Before we discuss the paper in class, you will meet in groups to discuss the paper and write a concise response to a few high-level questions about the paper. To avoid the same groups for each paper, you may be in a group with a student at most once.
If you would like a regrade of an assignment or exam, you must email me your request within 1 week from when grades are announced.
Academic misconduct such as cheating will not be tolerated. The work you submit in this class is expected to be your own. If you submit work that has in part or in whole been copied from some published or unpublished source (including current or former students), or that has been prepared by someone other than you, or that in any way misrepresents somebody else’s work as your own, you will face severe discipline by the university. (Adapted from text appearing at the Office of Student Conduct page.)
Any detected cases of cheating will be pursued. Penalties can include: receiving a zero on the assignment (the minimum penalty), failing the course, having a note placed in your permanent academic record, suspension, and ultimately expulsion.
See Penn’s Code of Academic Integrity for more information.
This schedule is subject to change
|Date||Topic||Textbook reading||Assignment due|
|Thu 29 Aug||Introduction [pdf]|
|Tue 3 Sep||Trends [pdf], ISAs [pdf]||1.1|
|Wed 4 Sep||paper review #1 due at midnight|
|Thu 5 Sep||"|
|Tue 10 Sep||Technology [pdf]|
|Thu 12 Sep||"||9.1|
|Tue 17 Sep||Performance [pdf]||1.2-1.4|
|Wed 18 Sep||paper review #2 due at midnight|
|Thu 19 Sep||"|
|Fri 20 Sep||homework #1 due at midnight|
|Mon 23 Sep||paper review #3 due at midnight|
|Tue 24 Sep||Pipelining [pdf]||2.1|
|Thu 26 Sep||"||4.1|
|Tue 1 Oct||"|
|Wed 2 Oct||homework #2 due at midnight|
|Thu 3 Oct||Caches [pdf]||2.2|
|Tue 8 Oct||"||6.1, 6.2, 6.3.1|
|Wed 9 Oct||paper review #4 due at midnight|
|Thu 10 Oct||no class, Fall Break|
|Tue 15 Oct||Virtual Memory [pdf]||2.3, 6.1.1||midterm review from 6-8pm in Meyerson B3|
|Wed 16 Oct||homework #3 due at midnight|
|Thu 17 Oct||Midterm Exam [solution+rubric]|
|Tue 22 Oct||midterm review|
|Thu 24 Oct||Virtual Memory|
|Tue 29 Oct||Superscalar [pdf]||3.1, 3.2, 3.5.1|
|Thu 31 Oct||Dynamic Scheduling [pdf]||4.2, 4.3, 5.3.3|
|Mon 4 Nov||homework #4 due at midnight|
|Tue 5 Nov||"||3.3.1-3.3.4|
|Thu 7 Nov||"||5.0, 5.1|
|Tue 12 Nov||"||5.2, 5.3.3|
|Thu 14 Nov||"||5.4, 5.5|
|Tue 19 Nov||Multicore [pdf]||7.0, 7.1.3, 7.2, 7.3|
|Wed 20 Nov||paper review #5 and homework #5: First Results due at midnight|
|Thu 21 Nov||"||7.4|
|Tue 26 Nov||"||8.2|
|Wed 27 Nov||homework #5 due at midnight|
|Thu 28 Nov||no class, Thanksgiving|
|Tue 3 Dec||Vectors [pdf]||7.5, 8.1|
|Thu 5 Dec||Multicore continued|
|Tue 10 Dec||Xbox1/PS4 [pdf]||homework #6 due at midnight|
|Wed 11 Dec||final review from 2-3:30pm in DRL A7|
|Monday 16 Dec||Final Exam, 6-8pm, Berger Auditorium|