André DeHon <andre@acm.org> Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering Electrical and System Engineering Computer and Information Science (secondary) University of Pennsylvania Chair of Computer Engineering Program Committee Director CyberSavvy Security Center Office: Levine 270 Office Hour: M4:00-5:00pm

IC Group (research page) Lab: Moore 315

André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering affiliated with Electrical and Systems Engineering (ESE) and Computer and Informance Science (CIS). Prof. DeHon is the founding chair of Penn's Computer Engineering (CMPE) program and the founding director of the CyberSavvy Research Center, a nationwide security initiative sponsored by DARPA. He also serves as chair of the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing. Prof. DeHon is a leading researcher in computer engineering, having established a strong foundation in engineering science for both reconfigurable computing and computer security. His Implementation of Computation Lab delves into how computations can be physically implemented through software and hardware co-design. Prof. DeHon's work focuses on designing adaptable, resilient, and efficient hardware architectures that can be dynamically reprogrammed to accommodate various computational tasks, alongside developing tools to support these architectures. His research emphasizes reconfigurable computing, FPGA (Field-Programmable Gate Array) architectures, interconnects, and aspects such as security, reliability, energy efficiency, and performance.

Research

Broadly, my research interests address this question, including physical substrates (VLSI, molecular, ...), programmable media (FPGAs, (multi-) processors, ...), mapping (compilation and CAD), system abstractions and dynamic management (run-time systems, OS, scheduling), and problem capture (programming languages).

Ongoing

• Chair of ACM SIGDA TC-FPGA -- Checkout our new portal.
  • FPGA and Reconfigurable Computing Hall-of-Fame
    • Article in IEEE Solid-State Circuits Magazine, Spring 2018
    • Class 2017--2024 done; nominate for 2025 Class

Recent Selection

• SEVER & PROTECT DARPA Security Award anchoring new CyberSavvy security center (actively recruiting new students)
• Class of 2023 IEEE Fellow
• 2020 IEEE-CS Mary Kenneth Keller Computer Science and Engineering Undergraduate Teaching Award
• The Density Advantage of Configurable Computing inducted into 2019 Class of TCFPGA Hall of Fame [Endorsement]
• Class of 2018 ACM Fellow

• REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs, in FPGA, February 2024.
• Asymmetry in Butterfly Fat Tree FPGA NoC in FPT, December 2023.
• ExHiPR: Extended High-level Partial Reconfiguration for Fast Incremental FPGA Compilation> in ACM TRETS.
• Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration, in FPT, December 2022.
• PLD: Fast FPGA Compilation to Make Reconfigurable Acceleration Compatible with Modern Incremental Refinement Software Development in ASPLOS, March 2022.
• SCALPEL: Exploring the Limits of Tag-enforced Compartmentalization in ACM JETC, January 2022.
• Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction in ACM CCS, November 2021.
• Automated Least-Privilege Analysis (μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts) in RAID, October 2021.
• XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion in FCCM, May 2021.
• Flightplan: Dataplane Disaggregation and Placement for P4 Programs in NSDI, April 2021.
• Fast Linking of Separately-Compiled FPGA Blocks without a NoC in ICFPT, December 2020.
• DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors in CoNEXT, December 2020.
• Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks in ICFPT, December 2019.
• Pipelined Parallel Finite Automata Evaluation in ICFPT, December 2019.
• Self-Adaptive Timing Repair in IEEE Design and Test, November/December 2017.
• The DOVER Edge in RICV-V Workshop, July 2016.
• Accurate Parallel Floating-Point Accumulation in IEEE Transactions on Computers, November 2016.
• DOVER: a Metadata-extended RISC-V in RISC-V Workshop, January 2016.
• Fundamental Underpinnings of Reconfigurable Computing Architectures in Proc. of the IEEE Special Issue on Reconfigurable Sysems, March 2015.
• Reconfigurable Computing Architectures in Proc. of the IEEE Special Issue on Reconfigurable Sysems, March 2015.
• Architectural Support for Software-Defined Metadata Processing in ASPLOS, March 2015.
• Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, edited book from Elsevier (available from amazon.com)
• For more complete and earlier publications, see longer list.

Courses

• Spring 2025: ESE 5370: Hardware Security
• Fall 2025: ESE 5320: System-on-a-Chip Architecture

• ESE 5320: System-on-a-Chip Architecture (Penn, Spring and Fall 2017, Fall 2018, Fall 2019, Fall 2020, Fall 2021, Fall 2022, 2023, 2024)
• ESE 1500: Digital Audio Basics (Penn, Spring 2018, Spring 2019, Spring 2020, Spring 2021, Spring 2022, Spring 2023)
• ESE3700: Circuit-Level Modeling, Design, and Optimization for Digital Systems, (Penn, Fall 2010, 2011, 2012, 2013, 2014)
• ESE534: Computer Organization, (Penn, Spring 2010, 2012, 2014, 2016)
• ESE250: Digital Audio Basics, (Penn, Fall 2009, Spring 2013) [evolved to ESE1500 above]
• ESE535: Electronic Design Automation (Penn, Spring 2008, 2009, 2011, 2013, 2015)
• see longer list for earlier courses

Writing

• Unified publication list
• Selected Themes:
  • Security
  • Fast FPGA Compilation
  • Energy of Computation
  • ``Messy'' Computing
  • Molecular-scale/Sublithographic Architecture
  • Interconnect
  • Compute Models and Design Patterns
  • MATRIX
  • DPGA
• Theses
• Assorted advice, reflections, recommended reading

Academic History

• CALTECH Assistant Professor of Computer Science 1999--2006
• UCB Postdoc 1996-1999
• MIT SB '90, SM '93, PhD '96
• LSMSA '86